1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same and, more particularly to a semiconductor memory device used as a non-volatile memory device and a method of manufacturing the same.
2. Description of the Related Art
FIGS. 24A to 24C show a conventional semiconductor non-volatile memory device, in which FIG. 24A shows a high breakdown voltage transistor, FIG. 24B shows a memory cell transistor, and FIG. 24C shows a 5 V system transistor. The memory cell transistor in FIG. 24B has a two-layered conductive film structure constituted by a floating gate and a control gate. The floating gate is formed by a first conductive film 14 and the control gate is formed by a second conductive film 17. The gate electrode of a 5 V system transistor at the periphery of the memory cell transistor is formed by the second conductive film 17.
An electrically programmable non-volatile memory device will be described below. The thicknesses of the insulating films in FIGS. 24A to 24C have the following relationship: T.sub.OX1 (a charge injection/extraction region or a tunnel region 15)&lt;T.sub.OX2 (a 5 V system gate insulating film 18)&lt;T.sub.OX3 (a high breakdown voltage gate insulating film 13). In manufacturing the memory, the high breakdown voltage insulating film 13 is formed on a semiconductor substrate 11, and an opening is formed to form the tunnel region 15 using normal photoetching. Thereafter, the first conductive film 14 is formed, a cell slit is formed by photoetching, and the first conductive region in a 5 V system region and the high breakdown voltage insulating film 13 are sequentially etched.
Thereafter, the 5 V system gate insulating film 18 10 is formed. At the same time, an insulating film 16 is formed on the floating gate. Furthermore, the second conductive film 17 is formed. In FIGS. 24A to 24C, reference numerals 12 denote diffusion layers each having a conductivity type opposite to that of the semiconductor substrate 11.
In the above-described prior art, an electrically erasable and programmable non-volatile memory (to be referred to as an EEPROM hereinafter) and a logic circuit (5 V system) are formed on the same substrate. The former has a two-layered conductive film gate structure, but the latter has a single conductive film gate, and three types of films consisting of an insulating film between the floating gate and the control gate, the high breakdown voltage gate insulating film, and the tunnel insulating film, and one type of the 5 V system insulating film, i.e., a total of four types of insulating films must be arranged in the EEPROM region. Therefore, the EEPROM and the logic circuit are not properly matched with each other on a single chip.